1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a read only memory having a NAND cell array.
2. Background of the Related Art
The integration density of a read only memory device has been increased from 8 mega-bits to 16 mega-bits, and a NAND type mask programmable read only memory device is attractive in view of integration density. FIG. 1 shows a part of the memory cell array incorporated in a prior art NAND type mask programmable read only memory device, and comprises a memory block 1 broken down into two memory sub-blocks 1a and 1b coupled in parallel between a bit line Y and a source line S. Though not shown in FIG. 1, the memory cell array further contains a large number of memory blocks which are arranged in rows and columns together with the memory block 1.
The memory sub-block 1a is implemented by a series combination of n-channel type switching transistors Qs1 and Qs2 and n-channel type memory transistors Qm1, Qm2 and Qm3, and the other memory sub-block 1b is also implemented by a series combination of n-channel type switching transistors Qs3 and Qs4 and n-channel type memory transistors Qm4, Qm5 and Qm6. Each of the n-channel type switching transistors Qs1 to Qs4 is operative in either enhancement or depletion mode, and doping is selectively carried out for the channel regions of the n-channel type switching transistors Qs1 to Qs4 so as to form the n-channel type depletion mode switching transistors Qs1 to Qs4.
Decoded signal lines Xs1 and Xs2 are coupled with the n-channel switching transistors Qs1 and Qs3 and with the n-channel switching transistors Qs2 and Qs4, respectively, and allows the n-channel type switching transistors Qs1 to Qs4 operative in either enhancement or depletion mode to selectively couple the memory sub-blocks 1a and 1b with the associated bit line Y. The n-channel type memory transistors Qm1 to Qm6 are also operative in either enhancement or depletion mode, and the n-channel enhancement mode memory transistors Qm1, Qm2, Qm4 and Qm6 and the n-channel depletion mode transistors Qm3 and Qm5 correspond to the logic levels opposite to each other.
In other words, the n-channel type memory transistors Qm1 to Qm6 serve as the memory cells respectively storing data bits in non-volatile manner. The enhancement mode memory transistors Qm1, Qm2, Qm4 and Qm6 are representative of data bits of logic "1" level, and the depletion mode memory transistors Qm3 and Qm5 are representative of data bits of logic "0" level. Doping selectively carried out for the channel regions also forms the depletion mode transistors. Word lines WL1, WL2 and WL3 are coupled with the n-channel type memory transistors Qm1 and Qm4, Qm2 and Qm5, and Qm3 and Qm6, and are selectively driven to positive high voltage level.
The prior art mask programmable read only memory device operates as follows. In order to select one of the memory sub-blocks 1a and 1b, the decoded signal lines Xs1 and Xs2 are selectively driven to positive high voltage level or 5 volts, and one of the decoded signal lines remains in low voltage level or zero volts. If the decoded signal line Xs1 is driven to the positive high voltage level, the memory sub-block 1b is coupled with the bit line Y. However, the decoded signal line Xs2 of the low voltage level causes the memory sub-block 1a to be isolated from the bit line Y.
Subsequently, remaining one of the word lines WL1 to WL3 in the low voltage level, the other word lines are driven to the positive high voltage level. The word line kept in the low voltage level selects one of the n-channel type memory transistors Qm1 to Qm3 from the selected memory sub-block 1a. If the selected memory transistor is operative in the depletion mode, any conductive channel takes place in the selected memory transistor, and the selected memory transistor cuts off the current path from the bit line Y to the source line S. However, the n-channel type depletion mode memory transistor allows current to flow from the bit line Y through the selected memory sub-block 1a to the source line S. Thus, the selected memory transistor either couples or block the source line from the bit line Y, and voltage level on the bit line Y is either decayed or kept depending upon the data bit represented by the selected memory transistor. The voltage level on the bit line Y is monitored to see whether the accessed data bit is either logic "1" or "0" level.
FIGS. 2 to 4 show a typical example of the NAND type mask programmable read only memory device, and the NAND type mask programmable read only memory device is fabricated on a p-type silicon substrate 2 lightly doped at 4.times.10.sup.16 /cm.sup.-3. A passivation film 3 of boron phosphosilicate glass or BPSG and the bit line Y of aluminum are removed from FIG. 2 for better understanding of the layout of the prior art mask programmable read only memory device. A thick field insulating film 4 are selectively grown on the major surface of the p-type silicon substrate 2, and defines an active area 5 in the major surface of the p-type silicon substrate 2. The thick field insulating film 4 is as thick as 6000 angstroms. The field insulating film is formed in the active area 5 as a layer.
The active area 5 is covered with a gate oxide film 6 which is as thin as 250 angstroms. On the gate oxide film 6 polysilicon strips 7a, 7b, 7c, 7d and 7e of 3000 angstroms in thickness are patterned. The polysilicon strips 7a to 7e respectively serve as the decoded signal lines Xs1 and Xs2 and the word lines WL1 to WL3, and provide the gate electrodes of the n-channel type switching transistors Qs1 to Qs4 and the gate electrode of the n-channel type memory transistors Qm1 to Qm6. The active area 5 under the gate electrodes serves as channel regions CQs1 to CQs4 of the n-channel type switching transistors Qs1 to Qs4 and channel regions CQm1 to CQm6 of the n-channel type memory transistors Qm1 to Qm6, and the channel regions CQs1 to cQs4 and CQm1 to CQm6 are selectively doped with n-type impurity atoms.
In this instance, the channel regions CQm3 and CQm5 are doped with n-type impurity atoms at 1.times.10.sup.17 /cm.sup.-3 so that the n-channel type memory transistors Qm3 and Qm5 is allowed to operate in the depletion mode. The other active area provides a cell drain region 5a, a cell source region 5b and source/drain regions 5c of the n-channel type switching transistors. Qs1 to Qs4 and the n-channel type memory transistors Qm1 to Qm6. The polysilicon strips 7a to 7e are covered with the passivation film 3, and a contact hole 3a is formed in the passivation film 3 and the gate oxide film 6. The contact hole thus passing through those films 3 and 6 allows the bit line Y to be held in contact with the cell drain region 5a as will be better seem from FIG. 3.
Thus, the memory cells of the prior art mask programmable read only memory device are directly arranged on the major surface of the p-type silicon substrate 2, and a problem is encountered in that the p-type silicon substrate 2 is enlarged in proportion to the number of the memory cells. In other words, when the integration density of the memory cell array is increased, the two-dimensional memory cell array requires a large-sized silicon substrate, and accordingly, decreases the production yield.
The above memory cell arrangement is described in U.S. Pat. No. 5,429,968 to Koyama. Further, similar arrangements of memory cells can be found in U.S. Pat. Nos. 5,031,011 to Aritome et al., 5,369,608 to Lim et al., 5,400,279 to Momodami et al. and 5,483,483 to Choi et al. In the arrangement of the aforementioned related and prior art NAND cell array, there is restriction in the resolution of lithography, and minimum line width. Further, as the field insulating film is formed in the active area 5 as a layer, there is limit to increase the integration of memory devices for obtaining a wider active region. Accordingly, integration of the semiconductor device is limited.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.